library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 

entity SerialToParallel is
    Port ( clk           : in  STD_LOGIC;                  
           reset         : in  STD_LOGIC;                 
           parallel_out  : out  STD_LOGIC_VECTOR (7 downto 0):=x"00"; 
           counter_in   : in  STD_LOGIC_VECTOR (3 downto 0); 
           serial_in    : in STD_LOGIC  );               
          
end SerialToParallel;

architecture Behavioral of SerialToParallel is
    signal STP : STD_LOGIC_VECTOR (7 downto 0); 

begin
    process(counter_in, reset,serial_in)
    --process(counter_in, reset)
    begin
        if reset = '1' then parallel_out <= "00000000"; 
            
        else

            case counter_in is
                when "0000" =>
			parallel_out<=STP ;
                   STP(0) <= serial_in; 
                when "0001" =>
                   STP(1) <= serial_in; 
                when "0010" =>
                   STP(2) <= serial_in; 
                when "0011" =>
                   STP(3) <= serial_in; 
                when "0100" =>
                   STP(4) <= serial_in; 
                when "0101" =>
                   STP(5) <= serial_in; 
                when "0110" =>
                   STP(6) <= serial_in; 
                when "0111" =>
                   STP(7) <= serial_in; 
		   
                when others =>
		   STP<= "00000000";
                     
            end case;
            
        end if;

    end process;

end Behavioral;
